PCI

Hello.

This week we are going to talk about PCI. PCI has from 0 up to 254 buses. On each bus you can have devices (maximum 32). The device can have many functions (up to 8). These functions could be useful if you are using a device which has multiple functionality. For example a Video acquisition card could have a function 0 for video acquisition and a function 1 for sound acquisition, etc etc... Some systems, like Linux have some abstraction over pci to handle big super computer configuration that has more than 256 pci. For that they use domains of buses which can have 256 buses each.

Each PCI slot has four interrupts possible (One per interrupt pin (A to D)).

PCI configuration space.

For a set of bus:device:functions you have a trame of 256 bits of data. This trame is called configuration space. the config space looks like :

Warning PCI registers are always little endian.

All the values present in this 256 bits chunk can be read or written (I think that some value are just read-only like the vendor ID or product ID).

Base address is an interesting value because it helps us to know the type of registers (IOports or memory). It helps us to know where the registers start in memory or iospace and where it ends.

For irq the line is present in the 60th bit of the chunk. This bit is set to 0 if the device doesn't support IRQ.